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RT8206A/b 1 ds8206a/b-04 march 2011 www.richtek.com ordering information note : richtek green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. high-efficiency, main power supply controllers for notebook computers general description the RT8206A/b dual step-down, switch-mode power- supply (smps) controller generates logic-supply voltages in battery-powered systems. the RT8206A/b includes two pulse-width modulation (pwm) controllers fixed at 5v/ 3.3v or adjustable from 2v to 5.5v. an optional external charge pump can be monitored through secfb (RT8206A). this device also features a linear regulator providing a fixed 5v output. the linear regulator provides up to 70ma output current with automatic linear-regulator bootstrapping to the byp input. the RT8206A/b includes on-board power-up sequencing, the power-good outputs, internal soft-start, and internal soft-discharge output that prevents negative voltages on shutdown. a constant on-time pwm control scheme operates without sense resistors and provides 100ns response to load transients while maintaining a relatively constant switching frequency. the unique ultrasonic mode maintains the switching frequency above 25khz, which eliminates noise in audio applications. other features include diode- emulation mode (dem), which maximizes efficiency in light-load applications, and fixed-frequency pwm mode, which reduces rf interference in sensitive application. the RT8206A/b is available in the wqfn-32l 5x5 package. features z z z z z wide input voltage range 6v to 25v z z z z z dual fixed 5v/3.3v outputs or adjustable from 2v to 5.5v, 1.5% accuracy z z z z z secondary feedback input maintains charge pump voltage (RT8206A) z z z z z independent enable and power good z z z z z 5v fixed ldo output : 70ma z z z z z 2v reference voltage 1% : 50ua z z z z z constant on-time control with 100ns load step response z z z z z frequency selectable via ton setting z z z z z r ds(on) current sensing and programmable current limit z z z z z selectable pwm, dem or ultrasonic mode z z z z z internal soft-start with 5 steps current limiting and soft-discharge z z z z z high efficiency up to 97% z z z z z 5mw quiescent power dissipation z z z z z thermal shutdown z z z z z rohs compliant and halogen free applications z notebook and sub-notebook computers z 3-cell and 4-cell li+ battery-powered devices package type qw : wqfn-32l 5x5 (w-type) lead plating system g : green (halogen free and pb free) rt8206 a : with secfb b : without secfb
RT8206A/b 2 ds8206a/b-04 march 2011 www.richtek.com typical application circuit wqfn-32l 5x5 rt8206b pin configurations wqfn-32l 5x5 RT8206A ref boot2 nc vin ldo nc vcc secfb boot1 lgate1 pvcc gnd pgnd lgate2 phase2 vout2 fb2 ilim2 pgood2 en2 ugate2 phase1 fb1 byp vout1 ilim1 pgood1 en1 ugate1 enldo 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9101112 14 13 28 27 26 25 24 22 23 32 31 30 29 gnd 33 ton skip ref boot2 nc vin ldo nc vcc nc boot1 lgate1 pvcc gnd pgnd lgate2 phase2 vout2 fb2 ilim2 pgood2 en2 ugate2 phase1 fb1 byp vout1 ilim1 pgood1 en1 ugate1 enldo 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9101112 14 13 28 27 26 25 24 22 23 32 31 30 29 gnd 33 ton skip (top view) figure 1. fixed voltage regulator RT8206A/b phase1 lgate1 boot1 ugate1 vout1 v o u t 1 5 v vin ref pgood2 byp pgood1 secfb/nc p v c c r 6 en2 en1 enldo ton 1 0 0 k vcc c 9 1 f on off skip gnd 1 2 3 4 6 21, exposed pad (33) 20 18 17 16 15 9 10 14 13 28 27 29 phase2 lgate2 pgnd boot2 ugate2 vout2 v o u t 2 q2 l 2 c 1 1 c 1 7 3 . 3 v r 9 c 1 2 v i n 6 v t o 2 5 v 1 0 f 1 0 f 0 . 1 f r 1 0 c 1 4 26 25 24 22 23 30 q4 0 r 8 0 c 1 3 4 . 7 h 2 2 0 f q1 l 1 c 2 c 3 r 4 1 0 f 0 . 1 f r 5 c 4 q3 0 r 3 0 c 1 6 . 8 h 2 2 0 f cp c 5 0 . 1 f c 7 0 . 1 f d 1 d 2 d 3 d 4 c 6 0 . 1 f c 8 0 . 1 f ldo pvcc c 1 0 4 . 7 f 7 19 c 1 6 1 f r 7 0 r 1 1 2 0 0 k r 1 2 3 9 k r 1 4 3 . 9 c 1 8 0 . 1 f c 1 5 0 . 2 2 f p v c c r 1 3 1 0 0 k 5 v e n a b l e 3 . 3 v e n a b l e v i n l d o c o n t r o l f r e q u e n c y c o n t r o l p w m / d e m / u l t r a s o n i c ilim1 ilim2 12 31 fb2 fb1 11 32 r 1 1 8 0 k r 2 1 8 0 k c 1 9
RT8206A/b 3 ds8206a/b-04 march 2011 www.richtek.com figure 2. adjustable voltage regulator RT8206A/b phase1 lgate1 boot1 ugate1 vout1 v o u t 1 5 v vin ref pgood2 byp pgood1 secfb/nc p v c c r 6 en2 en1 enldo ton 1 0 0 k vcc c 9 1 f on off skip gnd 1 2 3 4 6 21, exposed pad (33) 20 18 17 16 15 9 10 14 13 28 27 29 phase2 lgate2 pgnd boot2 ugate2 vout2 v o u t 2 q2 l 2 c 1 1 c 1 7 3 . 3 v r 9 c 1 2 v i n 6 v t o 2 5 v 1 0 f 1 0 f 0 . 1 f r 1 0 c 1 4 26 25 24 22 23 30 q4 0 r 8 0 c 1 3 4 . 7 h 2 2 0 f q1 l 1 c 2 c 3 r 4 1 0 f 0 . 1 f r 5 c 4 q3 0 r 3 0 c 1 6 . 8 h 2 2 0 f cp c 5 0 . 1 f c 7 0 . 1 f d 1 d 2 d 3 d 4 c 6 0 . 1 f c 8 0 . 1 f ldo pvcc c 1 0 4 . 7 f 7 19 c 1 6 1 f r 7 0 r 1 1 2 0 0 k r 1 2 3 9 k r 1 4 3 . 9 c 1 8 0 . 1 f c 1 5 0 . 2 2 f p v c c r 1 3 1 0 0 k 5 v e n a b l e 3 . 3 v e n a b l e v i n l d o c o n t r o l f r e q u e n c y c o n t r o l p w m / d e m / u l t r a s o n i c ilim1 ilim2 12 31 fb2 fb1 11 32 r 1 1 8 0 k r 2 1 8 0 k c 1 9 r 1 5 1 5 k r 1 6 1 0 k c 2 3 c 2 0 0 . 1 f r 1 7 1 1 . 5 k r 1 8 1 0 k c 2 2 c 2 1 0 . 1 f
RT8206A/b 4 ds8206a/b-04 march 2011 www.richtek.com function block diagram function block diagram pwm controller (one side) smps2 pwm buck controller boot2 ugate2 phase2 lgate2 gnd pv cc vout2 fb2 ilim2 pgood2 smps1 pwm buck controller boot1 ugate1 phase1 lgate1 pv cc vout1 fb1 ilim1 pgood1 ldo thermal shutdown ref internal logic power-on sequence clear fault latch sw threshold vcc pvcc enldo en1 en2 ref ton skip byp vin ldo pgnd trig q t off 1-shot trig q 1-shot r t on + - comp - + fault latch + - + - 1.1 x v ref 0.7 x v ref + - 0.9 x v ref over-voltage under-voltage on-time compute vin ton vout ref fb pgood lgate ugate + - blanking time + - v cc + - + - current limit zero detector skip phase ilim ss time 25khz detector
RT8206A/b 5 ds8206a/b-04 march 2011 www.richtek.com functional pin description ref (pin 1) 2v reference output. bypass to gnd with a 0.22uf capacitor. ref can source up to 50ua for external loads. loading ref degrades fbx and output accuracy according to the ref load-regulation error. ton (pin 2) frequency select input. (vout1/vout2 switching frequency, respectively) : ton = vcc, (200khz / 250khz) ton = ref, (300khz / 375khz) ton = gnd, (400khz / 500khz) vcc (pin 3) analog supply voltage input for the pwm core. bypass to gnd with a 1uf ceramic capacitor enldo (pin 4) ldo enable input. the ref/ldo is enabled if enldo is within logic high level and disable if enldo is less than the logic low level. nc (pin 5, 8) no internal connection. vin (pin 6) power-supply input. vin is used for the constant on-time pwm one shot circuits. vin is also used to power the linear regulators. the linear regulators are powered by smps1 if vout1 is set greater than 4.66v and byp is tied to vout1. connect vin to the battery input and bypass with a 1uf capacitor. ldo (pin 7) linear-regulator output. ldo can provide a total of 70ma external loads. the ldo regulates a fixed 5v output. when the byp is within 5v switchover threshold, the internal regulator shuts down and the ldo output pin connects to byp through a 1.5 switch. bypass ldo output with a minimum of 4.7uf ceramic. byp (pin 9) byp is the switchover source voltage input for the ldo. vout1 (pin 10) smps1 output voltage-sense input. connect this pin to the smps1 output. vout1 is an input to the constant on-time-pwm one-shot circuit. it also serves as the smps1 feedback input in fixed-voltage mode. fb1 (pin 11) smps1 feedback input. connect fb1 to vcc or gnd for fixed 5v operation. connect fb1 to a resistive voltage- divider from vout1 to gnd to adjust output from 2v to 5.5v. ilim1 (pin 12) smps1 current-limit adjustment. the gnd ? phase1 current-limit threshold is 1/10th the voltage seen at ilim1 over a 0.5v to 2v range. there is an internal 5ua current source from vcc to ilim1. the logic current limit threshold is default to 100mv if ilim1 is higher than (vcc ? 1v). pgood1 (pin 13) smps1 power-good open-drain output. pgood1 is low when the smps1 output voltage is more than 7.5% below the normal regulation point or during soft-start. pgood1 is high impedance when the output is in regulation and the soft-start circuit has terminated. pgood1 is low in shutdown. en1 (pin 14) smps1 enable input. the smps1 will be enabled if en1 is greater than the logic high level and disabled if en1 is less than the logic low level. if en1 is connected to ref, the smps1 starts after the smps2 reaches regulation (delay start). drive en1 below 0.8v to clear fault level and reset the fault latches. ugate1 (pin 15) high-side mosfet floating gate-driver output for smps1. ugate1 swings between phase1 and boot1. phase1 (pin 16) inductor connection for smps1. phase1 is the internal lower supply rail for the ugate1 high-side gate driver. phase1 is the current-sense input for the smps1.
RT8206A/b 6 ds8206a/b-04 march 2011 www.richtek.com boot1 (pin 17) boost flying capacitor connection for smps1. connect to an external capacitor according to the typical application circuits. lgate1 (pin 18) smps1 synchronous-rectifier gate-drive output. lgate1 swings between pgnd and pvcc. pvcc (pin 19) pvcc is the supply voltage for the low-side mosfet driver lgatex. connect a 5v power source to the pvcc pin (bypass with 1uf mlcc capacitor to pgnd if necessary). there is an internal 10 connecting from pvcc to vcc. make sure that both vcc and pvcc are bypassed with 1uf mlcc capacitors. secfb (pin 20) (RT8206A) the secfb is used to monitor the optional external 14v charge pump. connect a resistive voltage-divider from the 14v charge pump output to gnd to detect the output. if secfb drops below the threshold voltage, lgate1 will be turned on for 300ns. this will refresh the external charge pump driven by lgate1 without over-discharging the output voltage. nc (pin 20) (rt8206b) no internal connection. gnd [pin 21, exposed pad (33)] analog ground for both smps and ldo. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. pgnd (pin 22) power ground for smps controller. connect pgnd externally to the underside of the exposed pad. lgate2 (pin 23) smps2 synchronous-rectifier gate-drive output. lgate2 swings between pgnd and pvcc. boot2 (pin 24) boost flying capacitor connection for smps2. connect this pin to an external capacitor according to the typical application circuits. phase2 (pin 25) inductor connection for smps2. phase2 is the internal lower supply rail for the ugate2 high-side gate driver. phase2 is the current-sense input for the smps2. ugate2 (pin 26) high-side mosfet floating gate-driver output for smps2. ugate2 swings between phase2 and boot2. en2 (pin 27) smps2 enable input. the smps2 will be enabled if en2 is greater than the logic high level and be disabled if en2 is less than the logic low level. if en2 is connected to ref, the smps2 starts after the smps1 reaches regulation (delay start). drive en2 below 0.8v to clear fault level and reset the fault latches. pgood2 (pin 28) smps2 power-good open-drain output. pgood2 is low when the smps2 output voltage is more than 7.5% below the normal regulation point or during soft-start. pgood2 is high impedance when the output is in regulation and the soft-start circuit has terminated. pgood2 is low in shutdown. skip (pin 29) smps operation mode control. skip = gnd : dem operation skip = ref : ultrasonic mode operation skip = vcc : pwm operation. vout2 (pin 30) smps2 output voltage-sense input. connect this pin to the smps2 output. vout2 is an input to the constant on-time-pwm one-shot circuit. it also serves as the smps2 feedback input in fixed-voltage mode. ilim2 (pin 31) smps2 current-limit adjustment. the gnd ? phase2 current-limit threshold is 1/10th the voltage seen at ilim2 over a 0.5v to 2v range. there is an internal 5ua current source from vcc to ilim2. the logic current limit threshold is default to 100mv value if ilim2 is higher than (vcc ? 1v).
RT8206A/b 7 ds8206a/b-04 march 2011 www.richtek.com fb2 (pin 32) smps2 feedback input. connect fb2 to vcc or gnd for fixed 3.3v operation. connect fb2 to a resistive voltage- divider from vout2 to gnd to adjust output from 2v to 5.5v.
RT8206A/b 8 ds8206a/b-04 march 2011 www.richtek.com recommended operating conditions (note 4) z input voltage, v in ------------------------------------------------------------------------------------------------------ 6v to 25v z junction temperature range ---------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z vin, enldo to gnd ---------------------------------------------------------------------------------------------- ? 0.3v to 30v z bootx to gnd ----------------------------------------------------------------------------------------------------- ? 0.3v to 36v z phasex to gnd dc --------------------------------------------------------------------------------------------------------------------- ? 0.3v to 30v <20ns ---------------------------------------------------------------------------------------------------------------- ? 8v to 38v z bootx to phasex ----------------------------------------------------------------------------------------------- ? 0.3v to 6v z vcc, enx, skip, ton, pvcc, pgoodx, to gnd ------------------------------------------------------- ? 0.3v to 6v z ldo, fbx, voutx, secfb, ref , ilimx to gnd ---------------------------------------------------------- ? 0.3v to (v cc + 0.3v) z ugatex to phasex dc --------------------------------------------------------------------------------------------------------------------- ? 0.3v to (pv cc + 0.3v) <20ns ---------------------------------------------------------------------------------------------------------------- ? 5v to 7.5v z lgatex, byp to gnd dc --------------------------------------------------------------------------------------------------------------------- ? 0.3v to (pv cc + 0.3v) <20ns ---------------------------------------------------------------------------------------------------------------- ? 2.5v to 7.5v z pgnd to gnd ------------------------------------------------------------------------------------------------------ ? 0.3v to 0.3v z power dissipation, p d @ t a = 25 c wqf n-32l 5x5 ---------------------------------------------------------------------------------------------------- 2.778w z package thermal resistance (note 2) wqfn-32l 5x5, ja ----------------------------------------------------------------------------------------------- 36 c/w wqfn-32l 5x5, jc ---------------------------------------------------------------------------------------------- 7 c/w z junction temperature --------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------ ----------------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------ ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) -------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ---------------------------------------------------------------------------------------------- 200v to be continued
RT8206A/b 9 ds8206a/b-04 march 2011 www.richtek.com to be continued electrical characteristics (v in = 12v, en1 = en2 = v cc , v byp = 5v, pv cc = 5v, v enldo = 5v, no load on ldo, vout1, vout2 and ref, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit input supply vin standby supply current i vin_sby v in = 6v to 25v, both smps off, enldo = 5v -- 180 250 a vin shutdown supply current i vin_shdh v in = 6v to 25v, enx = enldo = gnd -- 20 40 a quiescent power consumption both smpss on, fb1 = skip = gnd, fb2 = v cc , v ou t1 = byp = 5.3v, v ou t2 = 3.5v (note 5) -- 5 7 mw smps output and fb voltage vout1 output voltage in fixed mode v out1 v in = 6v to 25v, fb1= gnd, skip = 5v 4.975 5.05 5.125 v vout2 output voltage in fixed mode v out2 v in = 6v to 25v, fb2 = v cc , skip = 5v 3.285 3.33 3.375 v fbx in output adjustable mode fbx v in = 6v to 25v 1.975 2 2.025 v secfb voltage secfb v in = 6v to 25v (RT8206A) 1.92 2 2.08 v output voltage adjust range smps1, smps2 2 -- 5.5 v fbx adjustable-mode threshold voltage fixed or adj-mode comparator threshold 0.2 0.4 0.55 v either smps, skip = v cc , 0 to 5a -- ? 0.1 -- either smps, skip = ref, 0 to 5a -- ? 1.7 -- dc load regulation v load either smps, skip = gnd, 0 to 5a -- ? 1.5 -- % line regulation v line either smps, v in = 6v to 25v -- 0.005 -- %/v on time smps1 = 5.05v (200khz) 1895 2105 2315 ton = v cc smps2 = 3.33v (250khz) 999 1110 1221 smps1 = 5.05v (300khz) 1227 1403 1579 ton = ref smps2 = 3.33v (375khz) 647 740 833 smps1 = 5.05v (400khz) 895 1052 1209 on-time pulse width t ugatex ton = gnd smps2 = 3.33v (500khz) 475 555 635 ns minimum off-time t lgatex 200 300 400 ns ultrasonic mode frequency skip = ref 25 33 -- khz soft start soft-start time t ssx zero to full limit from enx enable -- 2 -- ms current sense current limit threshold (default) i limx = v cc , gnd ? phasex 90 100 110 mv current limit current source i limx 4.75 5 5.25 a
RT8206A/b 10 ds8206a/b-04 march 2011 www.richtek.com to be continued parameter symbol test conditions min typ max unit i lim adjustment range v ilimx = i limx r ilimx 0.5 -- 2 v v ilimx = 0.5v 40 50 60 v ilimx = 1v 90 100 110 current-limit threshold gnd ? phasex v ilimx = 2v 180 200 220 mv zero-current threshold skip = gnd or ref, gnd ? phasex -- 3 -- mv internal regulator and reference ldo output voltage v ldo byp = gnd, 6v < v in < 25v, 0 < i ldo < 70ma 4.9 5 5.1 v ldo output current i ldo byp = gnd, v in = 6v to 25v 70 -- -- ma ldo short-circuit current ldo = gnd, byp = gnd -- 200 300 ma ldo 5v switchover threshold to byp v byp falling edge, rising edge at byp regulation point 4.53 4.66 4.79 v ldo switchover equivalent resistance r sw ldo to byp, 10ma -- 1.5 3 ref output voltage v ref no external load 1.98 2 2.02 v ref load regulation i ref = 0 to 50ua -- 10 -- mv ref sink current ref in regulation 10 -- -- a uvlo rising edge -- 4.35 4.5 pvcc uvlo threshold pvcc falling edge 3.9 4.05 -- v power good pgoodx threshold fbx with respect to internal reference, falling edge, hysteresi s = 1% ? 11 ? 7.5 ? 4 % pgoodx propagation delay falling edge -- 10 -- s pgoodx leakage current high state, forced to 5.5v -- -- 1 a pgoodx output low voltage i sink = 4ma -- -- 0.3 v fault detection ovp trip threshold v fb_ovp fbx with respect to internal ref. 108 111 115 % ovp propagation delay fbx with 50mv overdrive -- 10 -- s uvp trip threshold fbx with respect to internal ref. 65 70 75 % uvp shutdown blanking time t shdn_uvp from enx enable -- 3 -- ms thermal shutdown thermal shutdown t sh dn -- 150 -- c thermal shutdown hysteresis -- 10 -- c logic input low level (internal fixed v outx ) -- -- 0.2 fb1/fb2 input voltage high level (internal fixed v out x ) v cc ? 1 -- -- v
RT8206A/b 11 ds8206a/b-04 march 2011 www.richtek.com note 1. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. p vin + p pvcc parameter symbol test conditions min typ max unit low level (dem) -- -- 0.8 ref level (ultrasonic mode) 1.8 -- 2.3 skip input voltage high level (pwm mode) 2.5 -- -- v v out1 / v out2 (400khz / 500khz) -- -- 0.8 v out1 / v out2 (300khz / 375khz) 1.8 -- 2.3 ton setting voltage v out1 / v out2 (200khz / 250khz) 2.5 -- -- v clear fault level / smps off level -- -- 0.8 delay start 1.8 -- 2.3 enx input voltage smps on level 2.5 -- -- v rising edge 1.2 1.6 2.0 enldo input voltage v enldo falling edge 0.94 1 1.06 v enldo = 0v or 25v ? 1 -- +3 enx = 0v or 5v ? 1 -- +1 ton, skip = 0v or 5v ? 1 -- +1 fbx = 0v or 5v ? 1 -- +1 input leakage current secfb = 0v or 5v (RT8206A) ? 1 -- +1 a internal boot switch internal boost charging switch on-resistance pvcc to bootx -- 20 -- power mosfet drivers ugatex driver sink/source current ugatex forced to 2v -- 2 -- a lgatex driver source current lgatex forc ed to 2v -- 1.7 -- a lgatex driver sink current lgatex forced to 2v -- 3.3 -- a ugatex on-resistance bootx to phasex forced to 5v -- 1.5 4 lgatex, high state -- 2.2 5 lgatex on-resistance lgatex, low state -- 0.6 1.5 lg rising -- 30 -- dead time ug rising -- 40 -- ns
RT8206A/b 12 ds8206a/b-04 march 2011 www.richtek.com typical operating characteristics vout2 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) ultrasonic mode v in = 25v, ton = v cc , en2 = v cc , en1 = gnd, enldo = v in , fb2 = gnd dem mode pwm mode vout2 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) ultrasonic mode v in = 7v, ton = v cc , en2 = v cc , en1 = gnd, enldo = v in , fb2 = gnd dem mode pwm mode vout1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) ultrasonic mode v in = 25v, ton = v cc , en2 = gnd, en1 = v cc , enldo = v in , fb1 = gnd dem mode pwm mode vout2 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) ultrasonic mode v in = 12v, ton = v cc , en2 = v cc , en1 = gnd, enldo = v in , fb2 = gnd dem mode pwm mode vout1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) ultrasonic mode v in = 12v, ton = v cc , en2 = gnd, en1 = v cc , enldo = v in , fb1 = gnd dem mode pwm mode vout1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) dem mode ultrasonic mode pwm mode v in = 7v, ton = v cc , en2 = gnd, en1 = v cc , enldo = v in , fb1 = gnd
RT8206A/b 13 ds8206a/b-04 march 2011 www.richtek.com vout2 switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 275 300 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) ultrasonic mode v in = 25v, ton = v cc , en2 = v cc , en1 = gnd, enldo = v in , fb2 = gnd dem mode pwm mode vout2 switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 275 300 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) ultrasonic mode v in = 12v, ton = v cc , en2 = v cc , en1 = gnd, enldo = v in , fb2 = gnd dem mode pwm mode vout2 switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 275 300 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) ultrasonic mode v in = 7v, ton = v cc , en2 = v cc , en1 = gnd, enldo = v in , fb2 = gnd dem mode pwm mode vout1 switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 0.001 0.01 0.1 1 10 load current (a) switching frequencyy (khz) ultrasonic mode v in = 25v, ton = v cc , en2 = gnd, en1 = v cc , enldo = v in , fb1 = gnd dem mode pwm mode vout1 switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) ultrasonic mode v in = 7v, ton = v cc , en2 = gnd, en1 = v cc , enldo = v in , fb1 = gnd dem mode pwm mode vout1 switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) ultrasonic mode v in = 12v, ton = v cc , en2 = gnd, en1 = v cc , enldo = v in , fb1 = gnd dem mode pwm mode
RT8206A/b 14 ds8206a/b-04 march 2011 www.richtek.com v ref vs. temperature 1.95 1.96 1.97 1.98 1.99 2.00 2.01 2.02 2.03 2.04 2.05 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature v ref (v) ( c) v in = 12.6v standby current vs. input voltage 198 200 202 204 206 208 210 212 214 216 7 9 11 13 15 17 19 21 23 25 input voltage (v) standby current (ua) standby current no load, en1 = en2 = gnd, enldo = v in no load battery current vs. input voltage 0.1 1 10 100 7 9 11 13 15 17 19 21 23 25 input voltage (v) battery current (ma) ultrasonic mode ton = v cc , en1 = en2 = v cc , enldo = v in dem mode pwm mode shutdown current vs. input voltage 9 11 13 15 17 19 21 23 25 27 7 9 11 13 15 17 19 21 23 25 input voltage (v) shutdown current (ua) shutdown current no load on vout1, vout2, ldo and ref, en1 = en2 = gnd, enldo = gnd ldo output voltage vs. output current 5.02 5.024 5.028 5.032 5.036 5.04 0 10203040506070 output current (ma) output voltage (v) v in = 12v, en1 = en2 = gnd, enldo = v in v ref vs. output current 2.00300 2.00325 2.00350 2.00375 2.00400 2.00425 2.00450 2.00475 2.00500 -10 0 10 20 30 40 50 output current (ua) v ref (v) v in = 12v, en1 = en2 = gnd, enldo = v in
RT8206A/b 15 ds8206a/b-04 march 2011 www.richtek.com power on from vin time (400 s/div) ref (2v/div) ldo (5v/div) v in (10v/div) cp (10v/div) no load, v in = 12v, ton = v cc, en1 = v cc , en2 = gnd, enldo = v in power on from en1 time (1ms/div) i l1 (2a/div) v out1 (5v/div) en1 (5v/div) pgood1 (5v/div) ton = v cc, en1 = v cc , en2 = gnd, enldo = v in no load, v in = 12v, dem mode power on from en1 time (1ms/div) i l1 (2a/div) v out1 (5v/div) en1 (5v/div) pgood1 (5v/div) ton = v cc, en1 = v cc , en2 = gnd, enldo = v in no load, v in = 12v, pwm mode power on from en1 time (1ms/div) i l1 (2a/div) v out1 (5v/div) en1 (5v/div) pgood1 (5v/div) ton = v cc, en1 = v cc , en2 = gnd, enldo = v in i load = 4a, v in = 12v, pwm mode power on from en2 time (1ms/div) i l2 (2a/div) v out2 (5v/div) en2 (5v/div) pgood2 (5v/div) ton = v cc, en1 = gnd, en2 = v cc , enldo = v in no load, v in = 12v, dem mode power on from en2 time (1ms/div) i l2 (2a/div) v out2 (5v/div) en2 (5v/div) pgood2 (5v/div) ton = v cc, en1 = gnd, en2 = v cc , enldo = v in no load, v in = 12v, pwm mode
RT8206A/b 16 ds8206a/b-04 march 2011 www.richtek.com vout1 load transient response time (20 s/div) i l1 (5a/div) v out1_ac- coupled (50mv/div) lgate1 (5v/div) pwm mode, v in = 12v ton = v cc , skip = v cc , enldo = v in , fb1 = v cc power off from en1 time (10ms/div) v out1 (5v/div) en1 (10v/div) ugate1 (20v/div) lgate1 (5v/div) v in = 12v, ton = v cc , skip = v cc , enldo = v in power on from en2 (delay start) time (400 s/div) v out1 (2v/div) en1 (5v/div) v in = 12v, ton = v cc , enldo = v in en1 = ref en2 (5v/div) v out2 (2v/div) power on from en1 (delay start) time (400 s/div) v out1 (2v/div) en1 (5v/div) v in = 12v, ton = v cc , enldo = v in en2 = ref en2 (5v/div) v out2 (2v/div) vout2 load transient response time (20 s/div) i l2 (2a/div) v out2_ac- coupled (50mv/div) lgate2 (5v/div) pwm mode, v in = 12v ton = v cc , skip = v cc , enldo = v in , fb2 = v cc power on from en2 time (1ms/div) i l2 (2a/div) v out2 (5v/div) en2 (5v/div) pgood2 (5v/div) ton = v cc, en1 = gnd, en2 = v cc , enldo = v in i load = 4a, v in = 12v, pwm mode
RT8206A/b 17 ds8206a/b-04 march 2011 www.richtek.com ovp time (500 s/div) pgood1 (5v/div) vout1 (5v/div) pgood2 (5v/div) vout2 (5v/div) v in = 12v, ton = v cc , skip = gnd, enldo = v in uvp time (10 s/div) vout1 (5v/div) ugate1 (20v/div) i l1 (10a/div) lgate1 (5v/div) v in = 12v, ton = v cc , skip = v cc , enldo = v in power on in short circuit time (400 s/div) ugate1 (20v/div) vout1 (1v/div) lgate1 (5v/div) v out1 = short i l1 (5a/div) v in = 12v, ton = v cc , skip = v cc , enldo = v in
RT8206A/b 18 ds8206a/b-04 march 2011 www.richtek.com application information the RT8206A/b is a dual, high efficiency, mach response tm drv tm dual ramp valley mode synchronous buck controller. the controller is designed for low-voltage power supplies for notebook computers. richtek mach response tm technology is specifically designed for providing 100ns ? instant-on ? response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the drv tm mode pwm modulator is specifically designed to have better noise immunity for such a dual output application. the RT8206A/b achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode pwms. efficiency is further enhanced by its ability to drive very large synchronous rectifier mosfets. the RT8206A/b includes 5v (ldo) linear regulator which can step down the battery voltage to supply both internal circuitry and gate drivers. when v out1 voltage is above 4.66v, an automatic circuit turns off the linear regulator and powers the device from v out1 through byp pin connected to v out1 . pwm operation the mach response tm drv tm mode controller relies on the output filter capacitor's effective series resistance (esr) to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. refer to the function block diagram, the ugate driver will be turned on at the beginning of each cycle. after the internal one- shot timer expires, the ugate driver will be turned off. the pulse width of this one shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage range. another one-shot sets a minimum off-time (300ns typ.). the on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the current- limit threshold, and the minimum off-time one-shot has timed out. pwm frequency and on-time control the mach response tm control architecture runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. the high-side switch on-time is inversely proportional to the input voltage as measured by the v in , and proportional to the output voltage. the on-time is given by : on-time= k (v out / v in ) there ? k ? is set by the ton pin-strap connector (table 1). one-shot timing error increases for the shorter on- time setting due to fixed propagation delays that is approximately 15% at high frequency and the 10% at low frequency. the on-time guaranteed in the electrical characteristics tables is influenced by switching delays in the external high-side power mosfet. two external factors that influence switching-frequency accuracy are resistive drops in the two conduction loops (including inductor and pc board resistance) and the dead-time effect. these effects are the largest contributors to the change of frequency with changing load current. the dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times. it occurs only in pwm mode (skip = high) when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor's emf causes phase x to go high earlier than normal, extending the on- time by a period equal to the low-to-high dead time. for loads above the critical conduction point, the actual switching frequency is : f s = (v out +v drop1 ) / t on x (v in + v drop1 ? v drop2 ) the v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path; and t on is the on- time calculated by the RT8206A/b. table 1. ton setting and pwm frequency table ton ton = vcc ton = ref ton = gnd v out1 k-factor 5 s 3.33 s 2.5 s v out1 frequency 200khz 300khz 400khz v out2 k-factor 4 s 2.67 s 2 s v out2 frequency 250khz 375khz 500khz approximate k-factor error 10% 12.5% 15%
RT8206A/b 19 ds8206a/b-04 march 2011 www.richtek.com operation mode selection the RT8206A/b supports three operation modes: diode- emulation mode, ultrasonic mode, and forced-ccm mode. users can set operation mode by skip pin. all of the three operation modes will be introduced as follows. diode-emulation mode (skip = gnd) in diode-emulation mode, the RT8206A/b automatically reduces switching frequency at light-load conditions to maintain high efficiency. this reduction of frequency is achieved smoothly and without the increase of v outx ripple or load regulation. as the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low-side mosfet allows only partial of negative current when the inductor free-wheeling current reach negative. as the load current further decreases, it takes longer and longer to discharge the output capacitor to the level that requires for the next ? on ? cycle. the on-time is kept the same as that in the heavy-load condition. in reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction. the transition load point to the light-load operation can be calculated as following equation. in out load on (v v ) i t 2l ? ? i l t 0 t on slope = (v in -v out ) / l i l, peak i load = i l, peak / 2 figure 3. boundary condition of ccm/dem where t on is the given on-time. the switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency is made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). ultrasonic mode (skip = ref) connecting skip to ref activates a unique diode- emulation mode with a minimum switching frequency above 25khz. this ultrasonic mode eliminates audio- frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. in ultrasonic mode, the low-side switch gate-driver signal is or with an internal oscillator (>25khz). once the internal oscillator is triggered, the ultrasonic controller forces the lgatex high, turning on the low-side mosfet to induce a negative inductor current. at the point that the output voltage is higher than that of ref, the controller turns off the low-side mosfet (lgatex pulled low) and triggers a constant on-time (ugatex driven high). when the on-time has expired, the controller re-enables the low- side mosfet until the controller detects that the inductor current dropped below the zero-crossing threshold. forced-ccm mode (skip = v cc ) the low-noise, forced-ccm mode (skip = v cc ) disables the zero-crossing comparator, which controls the low-side switch on-time. this causes the low-side gate-driver waveform to become the complement of the high-side gate- driver waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop strives to maintain a duty ratio of v out /v in . the benefit of the forced- ccm mode is to keep the switching frequency fairly constant, but it comes at a cost : the no-load battery current can be 10ma to 40ma, depending on the external mosfets.
RT8206A/b 20 ds8206a/b-04 march 2011 www.richtek.com reference and linear regulator (ref, ldo and 14v charge pump) the 2v reference (ref) is accurate within 1% over temperature, making ref useful as a precision system reference. bypass ref to gnd with 0.22uf (min) capacitor. ref can supply up to 50ua for external loads. loading ref degrades fbx and output accuracy according to the ref load-regulation error. an internal regulator produces a fixed output voltage 5v. the ldo regulator can supply up to 70ma for external loads. bypass ldo with a minimum 4.7 f ceramic capacitor. when the output voltage of the v out1 is higher than the switchover threshold, an internal 1.5 n-channel mosfet switch connects v out1 to ldo through byp while simultaneously shutting down the internal linear regulator. in typical application circuit figure, the external 14v charge pump is driven by lgate1. when lgate1 is low, d1 charge c5 sourced from v out1 . c5 voltage is equal to v out1 minus a diode drop. when lgate1 transitions to high, the charge from c5 will transfer to c6 through d2 and charge it to v lgate1 plus v c5 . as lgate1 transients low on the next cycle, c6 will charge c7 to its voltage minus a diode drop through d3. finally, c7 charges c8 through d4 when lgate1 transi switched to high. cp output voltage is : cp = v out1 +2 x v lgate1 ? 4 x v d where : ` v lgate1 is the peak voltage of the lgate1 driver ` v d is the forward diode dropped across the schottkys secfb (RT8206A) is used to monitor the charge pump through resistive divider. in an event when secfb drops below 2v, the detection circuit forces the lgate1 on for 300ns to allow cp to recharge and the secfb rise above 2v. in the event of an overload on cp where secfb can not reach more than 2v, the monitor will be deactivated. the secfb pin has a 17mv of hysteresis so the ripple should be enough to bring the secfb voltage above the threshold by ~3x the hysteresis, or (3 x 17mv) = 51mv. reducing the cp decoupling capacitor and placing a small ceramic capacitor c19 (10pf to 47pf) in parallel will the upper leg of the secfb resistor feedback network (r11 of figure 3), will also increase the robustness of the charge pump. current-limit setting (ilimx) the RT8206A/b has a cycle-by-cycle current limiting control. the current-limit circuit employs a unique ? valley ? current sensing algorithm. if the magnitude of the current- sense signal at phasex is above the current-limit threshold, the pwm is not allowed to initiate a new cycle (figure 4). the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, inductor value, battery voltage, and output voltage. i l t 0 i l, peak i lim i load figure 4. valley current-limit the RT8206A/b uses the on-resistance of the synchronous rectifier as the current-sense element. use the worse- case maximum value for r ds(on) from the mosfet datasheet, and add a margin of 0.5%/ c for the rise in r ds(on) with temperature. the current-limit threshold is adjusted with an external resistor for the RT8206A/b at ilimx. the current-limit threshold adjustment range is from 50mv to 200mv. in the adjustment mode, the current-limit threshold voltage is precise to 1/10 the voltage seen at ilimx. the threshold defaults to 100mv when ilimx is connected to vcc. the logic threshold for switchover to the 100mv default value is higher than vcc ? 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the current-sense signal at phasex and gnd. mount or place the ic close to the low-side mosfet.
RT8206A/b 21 ds8206a/b-04 march 2011 www.richtek.com mosfet gate driver (ugatex, lgatex) the high-side driver is designed to drive high-current, low r ds(on) n-mosfet(s). when configured as a floating driver the instantaneous drive current is supplied by the flying capacitor between bootx and phasex pins. a dead time to prevent shoot through is internally generated between high-side mosfet off to low-side mosfet on, and low- side mosfet off to high-side mosfet on. the low-side driver is designed to drive high current low r ds(on) n-mosfet(s). the internal pulldown transistor that drives lgatex low is robust, with a 0.6 typical on- resistance. a 5v bias voltage is typically delivered from pvcc through ldo supply. the instantaneous drive current is supplied by an input capacitor connected between pvcc and gnd. for high-current applications, some combinations of high- and low-side mosfets might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with bootx, which increases the turn-on time of the high-side mosfet without degrading the turn-off time (figure 5). figure 5. reducing the ugatex rise time bootx ugatex phasex 10 v in soft-start a built-in soft-start is used to prevent surge current from power supply input after enx is enabled. the typical soft- start duration is 2ms period. the maximum allowed current limit is segmented in 5 steps : 20%, 40%, 60%, 80% and 100% during this period. the current limit steps can eliminate the v out folded-back in the soft-start duration. por and uvlo power-on reset (por) occurs when vin rises above approximately 3.7v (typ.), resetting the fault latches. pvcc undervoltage-lockout (uvlo) circuitry inhibits switching by keeping ugatex and lgatex low when pvcc is below 4v. the pwm outputs begin to ramp up once pvcc exceeds its uvlo threshold and enx is enable. power-good output (pgoodx) the pgoodx is an open-drain type output. pgoodx is actively held low in soft-start, standby, and shutdown. it is released when the voutx voltage is above than 92.5% of the nominal regulation point. the pgoodx goes low if it is 7.5% below its nominal regulator point. output over voltage protection (ovp) the output voltage can be continuously monitored for over voltage protection. when the output voltage of the voutx is 11% above the set voltage, over voltage protection will be enabled, if the output exceeds the over voltage threshold, over voltage fault protection will be triggered and the lgatex low-side gate drivers are forced high. this activates the low-side mosfet switch, which rapidly discharges the output capacitor and reduces the output voltage. once an over-voltage fault condition is set, it can only be reset by toggling enldo, enx, or cycling vin (por.) output under-voltage protection (uvp) the output voltage can be continuously monitored for under voltage protection. if the output is less than 70% of the error-amplifier trip voltage, under voltage protection will be triggered, and then both ugatex and lgatex gate drivers will be forced low. the uvp will be ignored for at least 3ms (typ.) after start-up or after a rising edge on enx. toggle enx or cycle vin (por) to clear the under-voltage fault latch and restart the controller. the uvp only applies to the buck outputs. thermal protection the RT8206A/b has a thermal shutdown protection function to prevent it from overheating. thermal shutdown occurs when the die temperature exceeds +150 c. all internal circuitry will be shut down during thermal shutdown. the RT8206A/b may trigger thermal shutdown if the ldo were not supplied from voutx, while input voltage is on vin and drawing current that is too high from the ldo. even if the ldo is supplied from voutx, overloading the
RT8206A/b 22 ds8206a/b-04 march 2011 www.richtek.com ldo causes large power dissipation on automatic switches, which may result in thermal shutdown. discharge mode when standby or shutdown mode occurs, or the output under voltage fault latch is set, the outputs discharge mode is triggered. during discharge mode, the output capacitor will be discharged to gnd through an internal 20 switch. shutdown mode the RT8206A/b smps1, smps2 and ldo have independent enabling control. drive enldo, en1 and en2 below the precise input falling-edge trip level to place the RT8206A/b in its low-power shutdown state. the RT8206A/b consumes only 20ua of quiescent current while in shutdown. when shutdown mode is activated, the reference turns off. the accurate 1v falling-edge threshold on the enldo can be used to detect a specific analog voltage level and shutdown the device. once in shutdown, the 1.6v rising-edge threshold activates, providing sufficient hysteresis for most application. power-up sequencing and on/off controls (enx) en1 and en2 control smps power-up sequencing. when the RT8206A/b applies in the single channel mode, en1 or en2 enables the respective outputs when enx voltage rising above 2.5v, and disables the respective outputs when enx voltage falling below 1.8v. connecting one of enx to vcc and the other one to ref can force the latter one output starts after the former one regulates. if both of enx forced to connect to ref, both outputs will always wait for the regulation of the other one. however, in this situation, neither of the two enx will be in regulation. output voltage setting (fbx) connect fb1 directly to gnd or vcc for a fixed 5v output (vout1). connect fb2 directly to gnd or vcc for a fixed 3.3v output (vout2). the output voltage can also be adjusted from 2v to 5.5v with a resistor-divider network (figure 6). the following equation is for adjusting the output voltage. choose r2 to be approximately 10k , and solve for r1 using the following equation : outx fbx r1 v = v 1 r2 ?? ?? + ?? ?? ?? ?? where v fbx is 2v (typ.). figure 6. setting voutx with a resistor-divider output inductor selection the switching frequency (on-time) and operating point (% ripple or l ir ) determine the inductor value as follows : on in out ir load(max) t(v - v) l = li where lir is the ratio of the peak-to-peak ripple current to the average inductor current. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although the powdered iron is inexpensive and can work well at 200khz. the core must be large enough to prevent it from saturating at the peak inductor current (i peak ) : i peak = i load(max) + [(l ir / 2) x i load(max) ] this inductor ripple current also impacts transient-response performance, especially at low v in ? v outx differences. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the peak amplitude of the output transient. the v sag also features a function of the output transient (v sag ) is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time : 2 outx load off(min) in sag in outx out outx off(min) in v (i ) l k t v v = vv 2c v k t v ?? ? + ?? ?? ?? ? ?? ? ?? ?? ?? ?? phasex lgatex r1 r2 v outx v in ugatex voutx fbx gnd where minimun off-time (t off(min) ) = 300ns (typ.) and k is from table 1.
RT8206A/b 23 ds8206a/b-04 march 2011 www.richtek.com p-p load(max) v esr i p-p ir load(max) v esr li sw esr out f 1 f = 2 esr c 4 in non-cpu applications, the output capacitor's size depends on how much esr is needed to maintain an acceptable level of output voltage ripple : there v p-p is the peak-to-peak output voltage ripple. organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. output capacitor stability stability is determined by the value of the esr zero relative to the switching frequency. the point of instability is given by the following equation : do not put high-value ceramic capacitors directly across the outputs without taking precautions to ensure stability. large ceramic capacitors can have a high- esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting voutx or the fbx divider close to the inductor. there are two related but distinct ways including double- pulsing and feedback loop instability in the unstable operation. double-pulsing occurs due to noise on the output or because the esr is too low that there is not enough voltage ramp in the output voltage signal. this ? fools ? the error comparator into triggering a new cycle immediately after the 300ns minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it may indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can trip the over-voltage protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. it helps to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under- or overshoot. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) - t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of rt8206, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wqfn-32l 5x5 packages, the thermal resistance ja is 36 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (36 c/w) = 2.778w for wqfn-32l 5x5 packages output capacitor selection the output filter capacitor must have low enough esr to meet output ripple and load-transient require ments, it?s commanded to keep the feedback voltage between 6 to 12mv. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no- load condition without tripping the ovp circuit. for cpu core voltage converters and other applications where the output is subject to violent load transients, the output capa citor?s size de pends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance :
RT8206A/b 24 ds8206a/b-04 march 2011 www.richtek.com layout considerations layout is very important in high frequency switching converter design. if the layout is designed improperly, the pcb could radiate excessive noise and contribute to the converter instability. the following points must be followed for a proper layout of RT8206A/b. ` connect rc low-pass filter from pvcc to vcc, the rc low-pass filter is composed of an external capacitor and an internal 10 resistor. bypass vcc to gnd with a capacitor 1uf is recommended. place the capacitor close to the ic, within 12mm (0.5 inch) if possible. ` keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high-voltage switching node. ` connections from the drivers to the respective gate of the high-side or the low-side mosfet should be as short as possible to reduce stray inductance. use 0.65mm (25 mils) or wider trace. the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8206A/b packages, the figure 7 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. figure 7. derating curves for RT8206A/b packages ` all sensitive analog traces and components such as voutx, fbx, gnd, enx, pgoodx, ilimx, vcc, and ton should be placed away from high-voltage switching nodes such as phasex, lgatex, ugatex or bootx nodes to avoid coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` gather ground terminal of vin capa citor(s), voutx capacitor(s), and source of low-side mosfets as close as possible. pcb trace defined as phasex node, which connects to source of high-side mosfet, drain of low- side mosfet and high-voltage side of the inductor, should be as short and wide as possible. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wqfn -32l 5x5 four layers pcb
RT8206A/b 25 ds8206a/b-04 march 2011 www.richtek.com table 2. operation mode truth table mode condition comment power-up pvcc < uvlo threshold transitions to discharge mode after a vin por and after ref becomes valid. ldo and ref remain active. run enldo = high, en1 or en2 enabled normal operation. over voltage protection either output > 111% of nominal level. lgatex is forced high. ldo and ref active. exited by vin por or by toggling enldo. under voltage protection either output<70% of nominal level after 3ms time-out expires and output is enabled. both ugatex and lgatex are forced low until enter discharge mode terminates. ldo and ref are active. exited by vin por or by toggling enldo, en1, or en2. discharge either smps output is still high in either standby mode or shutdown mode. during discharge mode, the output capacitor discharges to gnd through an internal 20 ? switch. standby enx < startup threshold, enldo = high. lgatex stays low. ldo and ref active. shutdown en1, en2, enldo=low all circuitry off. thermal shutdown t j > +150c all circuitry off. exit by vin por or by toggling enldo. table 3. power-up sequencing enldo (v) v en1 (v) v en2 (v) ldo 5v smps1 3v smps2 low x x off off off ?>2v? h igh low low on (after ref powers up) off off ?>2v? h igh low ref on (after ref powers up) off off ?>2v? h igh low high on (after ref powers up) off on ?>2v? h igh ref low on (after ref powers up) off off ?>2v? h igh ref ref on (after ref powers up) off off ?>2v? h igh ref high on (after ref powers up) on (after smps2 on) on ?>2v? h igh high low on (after ref powers up) on off ?>2v? h igh high ref on (after ref powers up) on on (after smps1 on) ?>2v? h igh high high on (after ref powers up) on on
RT8206A/b 26 ds8206a/b-04 march 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension e d 1 d2 e2 l b e a a1 a3 see detail a note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 4.950 5.050 0.195 0.199 d2 3.400 3.750 0.134 0.148 e 4.950 5.050 0.195 0.199 e2 3.400 3.750 0.134 0.148 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 32l qfn 5x5 package

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